This is a senior RTL design engineer position in the silicon design team within Visual and Parallel Computing Group (VPG) . VPG is responsible for delivering integrated graphics IP for Intel’s desktop and mobile processors. In this position, the person would be responsible for the micro-architecture and logic design of the clocking, reset, and power management of Intel�s integrated processor graphics designs.
This is a senior position with a wide range of responsibilities in logic design which will include:
- Working with the CPU and graphics micro-architects to define the clocking, reset, and power management logic
- Implementing the design in RTL
- Working with pre-silicon validation team on testplan and validation environments to ensure correctness of design
- Working with the physical design team to resolve timing issues
- Working with post-silicon teams to resolve silicon sightings.
- Clocking design responsibilities will include clock network design, PLL options, clock gating mechanisms. Will need to work closely with the physical design team and will require good understanding of – the overall floorplan and physical design constraints.
- Reset design needs close collaboration with the processor team as well as the graphics designers and DFx teams in order to establish the reset mechanism with deterministic exit from reset and to ensure proper fuse delivery to the graphics clusters.
- Power management will involve devising clock and power gating schemes for the design. This also involves determining activity factors of the design, ensuring optimal power state operations across different power modes, saving and restoring power contexts before and after power state transitions.
Desired Skills & Experience
You should possess a Bachelor or a Master of Engineering degree with 7 years or more of relevant industry experience.
Additional qualifications include:
- Experience with ASIC and/or SOC design flows.
- Experience in HDL design with Systemverilog or Verilog.
- Experience in RTL simulation and debug tools.
- Expertise in timing and area closure using Synopsys Synthesis tools.
- Scripting abilities.
Desirable qualifications:
- Knowledge of Processor and/or Graphics designs
- Experience in design and/or verification of clocking, reset, and power management logic
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Email: jobs@aarenconsultants.in
Posted by Aaren Consultants